Glossary

Terms used across the wiki. Skewed toward the ones that get used without explanation in producer earnings calls.

ASP — Average Selling Price. The metric memory producers report quarterly (per Gb-equivalent or per GB) to describe pricing.

Bit growth / bit shipments — DRAM/NAND output measured in bits rather than units. Producers report "bit growth" YoY as their primary volume metric, since chip density rises with each node.

CoWoS — Chip-on-Wafer-on-Substrate. TSMC's 2.5D advanced-packaging process. The HBM stack and the compute die are co-bonded on a silicon interposer using CoWoS. A primary upstream chokepoint for Nvidia and AMD AI accelerators.

CXMT — ChangXin Memory Technologies. Chinese DRAM producer; the only meaningful capacity entrant outside the Big 3 since Elpida's 2012 bankruptcy. Has not yet qualified HBM3e at Nvidia as of mid-2026.

DART — Data Analysis, Retrieval and Transfer system. The Korean Financial Supervisory Service's disclosure portal (dart.fss.or.kr). Korean-listed memory makers (Samsung Electronics, SK Hynix) file detailed financials here, including semi-annual customer-concentration disclosures the US-equivalent 20-F filings do not require.

DDR4 / DDR5 — Double Data Rate generations of commodity DRAM. DDR5 is the current generation for new servers and PCs.

EUV — Extreme Ultraviolet lithography. Used at advanced DRAM nodes (1α, 1β, 1γ, 1c) for critical layers. ASML is the sole supplier of EUV scanners.

FY24 / FY25 / FY26 — Fiscal-year notation. Note Micron's offset fiscal year: Micron's FY26 ends August 2026. Micron's Q1 FY26 call (December 2025) reports calendar Q4 2025 results. Nvidia's fiscal year is also offset; FY26 ends January 2026.

HBM — High Bandwidth Memory. 3D-stacked DRAM connected by TSVs (through-silicon vias) to a logic base die, bonded onto a silicon interposer via CoWoS or equivalent. The memory architecture used in all AI accelerators.

HBM3 / HBM3e / HBM4 — Generations. HBM3 (~80–192 GB per accelerator, 2023–2024); HBM3e (141–288 GB, 2024–2025); HBM4 (>288 GB, 2025–2026, with TSMC-fabricated logic base dies for SK Hynix).

LOI — Letter of Intent. A non-binding statement of intended terms. Used in the Stargate announcement (October 1, 2025) and most large-scale capacity discussions. Distinct from binding offtake.

LTA — Long-Term Agreement. A multi-year supply contract between memory producer and large buyer. In the current cycle: multi-year terms (3–5 years) with prepayments at 10–30% (some 30–40%) of contract value — vs. historical norm below 5%.

MI300X / MI325X / MI355X — AMD Instinct accelerator generations. 192 GB, 256 GB, 288 GB HBM respectively.

Node (1α / 1β / 1γ / 1c) — DRAM process generations, roughly 14nm → 12nm → 11nm → 10nm-class. Micron's nomenclature uses Greek (1-alpha, 1-beta, 1-gamma); Samsung and SK Hynix use 1a/1b/1c. Each shrink yields ~30%+ bit-density improvement.

Prepayment — Cash committed by a buyer in advance to reserve future supply. Historically <5% of contract value in DRAM. In the current cycle: 10–30%, sometimes 30–40%.

Purchase obligation — A 10-K disclosure line under contractual obligations. Records the present value of unconditional commitments to suppliers. Nvidia's was $50.3B as of October 26, 2025; AMD's was $12.2B at December 27, 2025.

Take-or-pay — A contract structure where the buyer must pay for the contracted quantity regardless of whether they take delivery. The functional substance of "specific commitments and stronger contractual structures" (Mehrotra Q1 FY26). Not explicitly disclosed in current LTAs.

TSV — Through-Silicon Via. Vertical electrical connections through stacked DRAM dies that make HBM possible. The packaging process step that turns a DDR-like wafer into an HBM-ready wafer. Currently the binding capacity constraint for HBM output — not wafer fab.

WSPM — Wafer Starts Per Month. The standard measure of fab capacity.

Bit growth vs wafer growth — Distinct concepts. Producers can grow bits faster than wafers by moving to a denser node. In the current cycle: industry bit-supply growth is capped at 10–15% annually (TrendForce); wafer additions are smaller and largely conversion (Samsung P4) rather than net new (SK Hynix M15X).