The fab and packaging pipeline

Every disclosed fab and packaging-line announcement, with realistic ramp dates. The short version: nothing announced relieves the 2025–2027 squeeze.

Micron

Idaho — ID1 (Boise)

• DRAM output begins late 2026 / 2H 2027 (sources differ; Micron's most recent framing says 2H 2027).
• ID2 accelerated via $1.2B grant reallocation from NY → ID.
• Total US program: $6.14B CHIPS direct funding, $200B over 20 years.
• Sources: Micron US expansion — Idaho; Tom's Hardware; NIST CHIPS — Micron Idaho.

New York (Clay, NY)

• First fab pushed; production "later" than Idaho per October 2025 update.
• Source: Tom's Hardware.
• This is the longest-tail US fab — concrete proof timelines are being stretched, not pulled forward.

SK Hynix

M15X (Cheongju, Korea) — wafer fab

• Pilot operations May 2026.
• Ramp 10K → 50K WSPM by Q4 2026; ~50–60K WSPM full mid-2027.
• Focus: HBM3E / HBM4 (1b DRAM).
• Sources: SEDaily; TheLec.
• Biggest near-term DRAM capacity add in the industry — but still gated by TSV/packaging downstream.

Cheongju advanced packaging fab

• $13B approved January 2026.
• World's largest HBM packaging plant; output by 2027.
• Sources: Financial Content; TrendForce.

West Lafayette, IN — US packaging

• $3.87B + $458M CHIPS direct funding.
• Groundbreaking 2H 2025; mass production 2H 2028.
• Sources: SK Hynix announcement; NIST CHIPS.
• First US HBM packaging — 2028 means three more years of US-side packaging tightness.

Samsung

Pyeongtaek P4 (1c DRAM conversion)

• Converting foundry capacity → 1c DRAM, primarily for HBM4.
• Target: 60K WSPM Q4 2025 → +80K Q2 2026 → +60K Q4 2026 = 200K total by end-2026, ~1/3 of Samsung's total DRAM output.
• Sources: TrendForce Nov 19, 2025; TrendForce Sep 12, 2025.

Pyeongtaek P5

• Construction resumed; mass production 2H 2028.
• Source: Digitimes.

Taylor, TX

• Logic/foundry (2nm/3nm), NOT DRAM/HBM. Risk production slipped to 2H 2026 / early 2027. $44B total.
• Sources: Tom's Hardware; TrendForce March 3, 2026.
• Important to dispel the assumption that Taylor relieves DRAM. It does not.

The shape of the pipeline

Reading across all of it:

1. Most "expansion" is conversion, not net new wafer capacity. Samsung's P4 1c ramp is converting logic capacity to DRAM. SK Hynix's M15X is new build, but most of its output is committed to HBM, which trades 3:1 against commodity DDR5.
2. The biggest dollar commitments of 2025–2026 are packaging announcements, not fab announcements. SK Hynix Cheongju $13B (packaging); SK Hynix West Lafayette $3.87B (packaging). This is the producers signaling where they think the constraint actually sits. See supply/hbm-packaging-bottleneck.md.
3. Packaging output dates are 2027–2028. None of the announced packaging capacity relieves the 2025–2026 squeeze.
4. US capacity is years away. Micron Idaho 2H 2027, Micron NY later, SK Hynix West Lafayette 2H 2028. The Big 3's domestic-Asia footprint will carry the cycle.

What would relieve the squeeze

In principle:

• A wave of new TSV-packaging lines coming online ahead of 2027. None disclosed.
• A demand miss large enough to dent the booking-side allocations described in demand/hyperscaler-buying.md and structure/ltas-and-prepayments.md.
• CXMT (China's ChangXin Memory Technologies) breaking through on HBM. CXMT has been a wildcard new entrant — see history of prior wildcards in history/prior-cycles.md. As of mid-2026, no HBM3e qualifications at Nvidia.

Absent one of those, the 2025–2027 squeeze is structural until late 2027 at the earliest.