HBM packaging is the bottleneck

The single most important physical fact in this cycle: the binding constraint on HBM is not DRAM wafer fab. It is TSV packaging and CoWoS interposer capacity at TSMC.

That has two consequences. First, "more wafers" does not solve the AI memory shortage — Micron and SK Hynix could double DRAM wafer starts tomorrow and still ship roughly the same HBM. Second, the producers know this, which is why their incremental capex announcements in 2025–2026 have been disproportionately packaging announcements, not fab announcements.

The 3:1 wafer trade ratio

Mehrotra, Micron Q1 FY26 call (Dec 17, 2025): "each gigabyte of HBM3E requires roughly three times the wafer capacity needed for the same amount of DDR5." Picked up verbatim in Tom's Hardware "HBM is Eating Your RAM" and TrendForce.

This is the load-bearing factoid for understanding why commodity DRAM is short even though no fab has burned down.

Where the 3× comes from

SemiAnalysis "Scaling the Memory Wall" decomposes it:

• Die-level area penalty. SK Hynix D1z DDR4 is 0.296 Gb/mm². HBM3 is 0.16 Gb/mm². That's a ~1.85× area hit at the die level before stacking.
• TSV (through-silicon-via) yield compounding. An HBM stack is 8 (HBM3), 12 (HBM3e 12-Hi), or in B300's case 12-high stacks of DRAM dies plus a base logic die, all interconnected by TSVs. Each stack step has yield <100%; the compounded yield loss across 8–12 stacking steps is significant.
• Base die. The bottom die of the stack is a logic die, not a DRAM die, and takes additional process steps.

Stack the area penalty and the yield compounding and you get ~3× wafer-equivalent consumption per GB shipped.

TSV capacity = HBM capacity

SemiAnalysis again: "HBM capacity is now quoted in terms of TSV capacity, as this is the main incremental set of processes that turn DDR wafers into HBM wafers."

This is why the fab expansions (Pyeongtaek P4/P5, Micron Idaho, SK Hynix M15X) ramp slowly relative to demand: even when the wafers are available, the TSV line in front of the back-end is the bottleneck.

CoWoS — the TSMC chokepoint

Even an HBM stack does not reach an Nvidia GPU until it is interposer-bonded to the compute die. That happens at TSMC's CoWoS line (Chip-on-Wafer-on-Substrate). CoWoS is at full capacity through 2027 per Fusion Worldwide's analysis — TSMC has doubled CoWoS capacity in 2024–2025 and is still selling out.

Implication: two upstream chokepoints sit at TSMC for HBM4 — CoWoS and the HBM4 logic base die (which TSMC fabricates for SK Hynix as of HBM4). If TSMC slips on either, HBM4 commitments are bricked regardless of DRAM-side readiness.

Why the producers are announcing packaging, not fab

The 2025–2026 capacity announcements that matter most are packaging:

• SK Hynix Cheongju advanced packaging fab — $13B approved January 2026; world's largest HBM packaging plant; output by 2027. (Financial Content; TrendForce.)
• SK Hynix West Lafayette, IN — $3.87B advanced packaging plant + $458M CHIPS funding; groundbreaking 2H 2025; mass production 2H 2028. (SK Hynix announcement; NIST CHIPS page.)

That these are the headline capacity announcements — bigger than any DRAM fab announcement of 2025–2026 — is the producers' own admission of where the constraint sits.

What this means for the squeeze

• No 2025–2027 supply relief is possible from any disclosed packaging announcement — the Cheongju packaging plant outputs in 2027, West Lafayette in 2H 2028.
• More fab wafers don't solve the shortage — the TSV line in front of the back-end is the limit.
• Every HBM gigabyte costs three commodity-DRAM gigabytes of wafer-equivalent capacity. The price effect on commodity DDR5 (+~95% Q1 2026 contract price) is the direct downstream consequence.

See supply/fab-pipeline.md for the full fab and packaging ramp schedule, and demand/hyperscaler-buying.md for the booking-side view.